Many high-speed communications interfaces must be able to operate in a low-speed mode for some applications or platforms. For example, a laptop computer with limited power supplies and very high-speed memory components must have a low-speed mode in which the memory interface uses less power. Other reasons interfaces may be required to transition between low-speed modes and high-speed modes include user selection of one mode or another for a particular application or circumstance. Yet another reason is that in various circumstances the frequency of timing circuitry, for example phase locked loops (PLLs) may be changed, but some timing circuitry cannot change frequency during high-speed operation. The timing circuitry must be transitioned to a low-speed, in which the frequency is changed, and then the timing circuitry is transitioned to a high-speed mode again. In prior systems, this can cause significant performance degradation.
One example of a high-speed memory device is a double date rate dynamic random access memory (DRAM). Some DRAMs operate using high frequency (e.g. 1 GHz) sampling clock signals (also referred to as sampling clocks) that are generated from a single clock with a lower frequency (e.g., 500 MHz). The sampling clocks can be eight clocks, each separated by 45 degrees of phase. Generating the sampling clock generally requires power-consuming analog timing circuitry, e.g., a clock multiplier circuit or device, such as a delay locked loop (DLL) or phase locked loop (PLL). In the low speed mode, a digital timing circuit, such as a clock divider, which uses much less power than the clock multiplier, is typically used to divide the 500 MHz clock, for example to generate four 125 MHz clocks, each separated by 90 degrees of phase.
Switching from high-speed mode to low-speed mode generally does not require a significant bus idle time. The clock multiplier circuitry is turned off and the sampling clocks are generated by the digital clock divider circuitry. However, switching from low-speed mode to high-speed mode conventionally results in a significant amount of bus idle time during which no commands can be sent on the bus. This is illustrated in FIG. 1, which shows a transition between commands being sent by a controller during low-speed mode and high-speed mode. A shown in FIG. 1, a command or group of commands 102 are send during low-speed mode 106. The beginning of the transition, which is marked by a PLL-off cycle 103, can be followed by approximately 20,000 cycles of idle time 105. This idle time is caused primarily by the need to wait for the analog timing circuitry to power up and produce accurate, stable edges, after which time commands 104 can be sent in high-speed mode 108. This delay may cause unacceptable performance degradation. For example, in a graphics system it may not be possible to meet the monitor refresh requirements, making it impossible to provide a continuous stream of display information during a power state transition. For a central processing system (CPU), the thousands of idle clock cycles represent significant lost performance, and can result in a failure to meet a real time constraint.